Performance evaluation by evlauating performance

Performance evaluation.

0. Acknowledgments 8. Performance 6.2. Performance Evaluation

We have demonstrated that a self-timed on-chip cache can be produced and readily interfaced to an asynchronous microprocessor. In some parts of the design the asynchro-nous style provides a distinct advantage over a conventional , synchronous approach. An example of this is the mechanism used to reduce power consumption by switching off the RAM sense amplifiers when they are known to have produ...

Input Guided Performance Evaluation

Performance evaluation is a difficult and very challenging task. In spite of many discussions in the literature, e.g., (Haralick et al., 1994), and well understood goals, e.g., (Christensen and Förstner, 1997; Haralick, 1994), there is a wide gap between what performance assessment using simple, synthetic data predicts and what is obtained when the same algorithms are applied to real data. The ...

Computer Performance Evaluation: Preface

This issue of the Computer Journal is a special issue of the 6th European Performance Engineering Workshop (EPEW 2009), held at Imperial College London during 9–10 July 2009. EPEW has a successful record of gathering performance modelling, analysis and experience papers over the past 7 years and EPEW 2009 was no exception. EPEW 2009 was the first in the EPEW series to be held in the UK, followi...

SMP Virtualization Performance Evaluation

Multiprocessor virtual machines (VMs) allow guest operating systems to use symmetric multiprocessing (SMP) in a VM. However, the use of SMP in a VM complicates CPU scheduling by the virtual machine monitor and can significantly increase the performance overhead of virtualization. This paper analyzes the performance of SMP virtualization used in two leading virtualization systems: VMware ESX 3.5...